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general description the mx28f2100b is a 2-mega bit flash memory or- ganized as 256k bytes of 8 bits or 128k words of 16 bits switchable. mxic's flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. the mx28f2100b is packaged in 44-pin sop and 48-pin tsop (i ). it is designed to be reprogrammed and erased in-system or in-standard eprom programmers. the standard mx28f2100b offers access times as fast as 70ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx28f2100b has separate chip enable (ce) and output enable (oe ) controls. mxic's flash memories augment eprom function- ality with in-circuit electrical erasure and programming. the mx28f2100b uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. mxic flash technology reliably stores memory con- tents even after 10,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combi- nation of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx28f2100b uses a 12.0v 7% vpp supply to features ? 262,144x8/131,072x16 switchable ? fast access time: 70/90/120ns ? low power consumption C 50ma maximum active current C 100ua maximum standby current ? programming and erasing voltage 12v 7% ? command register architecture C byte/word programming (50 us typical) C auto chip erase 5 sec typical (including preprogramming time) C block erase (any one from 5 blocks:16k-byte x1, 8k-byte x2, 96k-byte x1, and 128k-byte x1) C auto erase with erase suspend capability 1 ? status register feature for device status detection ? auto erase (chip & block) and auto program C status registers ? 10,000 minimum erase/program cycles ? latch-up protected to 100ma from -1 to vcc+1v ? package type: C 44-pin sop C 48-pin tsop (type 1) perform the high reliability erase and auto program/ erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. p/n: pm0382 rev. 1.5, mar. 24, 1998 block structure 1ffffh 16 k-byte block a16~a0 8 k-byte block 8 k-byte block 96 k-byte block 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 128 k-byte block 00000h word mode (x16) memory map *byte mode operation should include a-1(lsb) for addressing preliminary mx28f2100b 2m-bit [256k x 8/128k x 16] cmos flash memory
2 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 pin configurations 44 sop(500 mil) tsop (type 1) (12mm x 20mm) (normal type) symbol pin name a0~a16 address input q0~q14 data input/output q15/a-1 q15(word mode)/lsb addr(byte mode) ce chip enable input we write enable input byte word/byte selction input rp reset/deep power down oe output enable input vpp power supply for program and erase vcc power supply pin (+5v) gnd ground pin pin description: 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 vpp nc nc a7 a6 a5 a4 a3 a2 a1 a0 ce gnd oe q0 q8 q1 q9 q2 q10 q3 q11 rp we a8 a9 a10 a11 a12 a13 a14 a15 a16 byte gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc mx28f2100b a15 a14 a13 a12 a11 a10 a9 a8 nc nc we rp vpp nc nc nc nc a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe gnd ce a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx28f2100b
3 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx28f2100b flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 q15/a-1 a0-a16 ce oe we byte rp
4 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic programming the mx28f2100b is byte/word programmable using the automatic programming algorithm. the automatic programming algorithm does not require the system to time out or verify the data programmed. the typical room temperature chip programming time of the mx28f2100b is less than 5 seconds. automatic chip erase the entire chip is bulk erased using 10 ms erase pulses according to mxic's high reliability chip erase algorithm. typical erasure at room temperature is accomplished in less than five seconds. the device may also be erased using the automatic erase algorithm. the automatic erase algorithm automati- cally programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internally. automatic block erase the mx28f2100b is block(s) erasable using mxic's auto block erase algorithm. block erase modes allow one of 5 blocks of the array to be erased in one erase cycle. the automatic block erase algorithm automati- cally programs the specified block(s) prior to electrical erase. the timing and verification of electrical erase are controlled internal to the device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write a program set-up command and a program command (program data and address). the device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. a status register scheme pro- vides feedback to the user as to the status of the programming operation. mxic's automatic erase algorithm requires the user to only write an erase set-up command and an erase command. the device will automatically pre-program and verify the entire array. then the device automati- cally times the erase pulse width, provides the erase verify, and counts the number of sequences. a status register provides feedback to the user as to the status of the erase operation. it is noted that after an erase set-up command, if the next command is not an erase command, then the state-machine will set both the program status and erase status bits of the status register to a "1", place the device into the read status register state, and wait for another command. commands are written to the command register using standard microprocessor write timings. register con- tents serve as inputs to an internal state-machine which controls the erase and programming circuitry. during write cycles, the command register internally latches address and data needed for the programming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data is latched on the rising edge of we . mxic's flash technology combines years of eprom experience to produce the highest levels of quality, relia- bility, and cost effectiveness. the mx28f2100b electri- cally erases all bits within a sector or chip simultaneously using fowler-nordheim tunneling. the array is pro- grammed one byte/word at a time using the eprom programming mechanism of hot electron injection. during a program cycle, the state-machine will control the program sequences and command register will not re- spond to any command set. during a sector/chip erase cycle, the command register will respond to erase sus- pend command. after erase suspend completed, the device stays at status register read state. after the state machine has completed its task, it will allow the command register to respond to its full command set. automatic erase algorithm
5 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 table 1. software command definitions command bus first bus cycle second bus cycle cycle mode address data mode address data x8 x16 x8 x16 read memory array 1 write x ffh xxffh --- --- --- --- setup auto program/ 2 write x 10h xx10h write program program program auto program or 40h or xx40h address data data setup erase/erase(chip) 2 write x 20h xx20h write x 20h xx20h setup erase/erase(block) 2 write x 60h xx60h write block 60h xx60h address setup auto erase/ 2 write x 30h xx30h write x 30h xx30h auto erase(chip) setup auto erase/ 2 write x 20h xx20h write block d0h xxd0h auto erase(block) address erase verify 2 write verify a0h xxa0h read x verify verify address data data read device identifier code 2 write x 90h xx90h read adi ddi ddi erase suspend 1 write x b0h xxb0h --- --- --- --- erase resume 1 write x d0h xxd0h --- --- --- --- read status register 2 write x 70h xx70h read x srd srd clear status register 1 write x 50h xx50h --- --- --- --- command definitions placing high voltage on the vpp pin enables read/write operations. device operations are selected by writing specific data patterns into the command register. ta- ble 1 defines these mx28f2100b register commands. table 2 defines the bus operations of mx28f2100b. note: 1. write and read mode are defined in mode selection table. 2. adi = address of device identifier; a0 = 0 for manufacture code, a0 = 1 for device code. ddi = data of device identifier : c2h for manufacture code, 2bh for device code(byte = vil) ; 00c2h for manufacture code, 002bh for device code(byte =vih) x = x can be vil or vih srd = status register data
6 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 table 2. mx28f2100b bus operation pins a0 a9 ce oe we vpp data i/o mode d0~d7 d8~d14 d15/a-1 read a0 a9 vil vil vih vppl data out hi-z a-1 output disable x x vil vih vih vppl hi-z hi-z x byte read-only standby x x vih x x vppl hi-z hi-z x mode read silicon id(mfr)(2) vil vid(3) vil vil vih vppl data=c2h hi-z vil byte read silicon id(device)(2) vih vid(3) vil vil vih vppl data=2bh hi-z vil = l read a0 a9 vil vil vih vpph data out(4) hi-z a-1 read/write output disable x x vil vih vih vpph hi-z hi-z x standby(5) x x vih x x vpph hi-z hi-z x write a0 a9 vil vih vil vpph data in(6) x a-1 read a0 a9 vil vil vih vppl data out data out data out read-only output disable x x vil vih vih vppl hi-z hi-z hi-z word standby x x vih x x vppl hi-z hi-z hi-z mode read silicon id(mfr)(2) vil vid(3) vil vil vih vppl data=c2h data=00h(8) 0b byte read silicon id(device)(2) vih vid(3) vil vil vih vppl data=2bh data=00h(8) 0b = h read a0 a9 vil vil vih vpph data out(4) data out data out read/write output disable x x vil vih vih vpph hi-z hi-z hi-z standby(5) x x vih x x vpph hi-z hi-z hi-z write a0 a9 vil vih vil vpph data in(6) data in(6) data in(6) notes: 1. vppl may be grounded, a no-connect with a resistor tied to ground, or < vcc + 2.0v. vpph is the programming voltage specified for the device. when vpp = vppl, memory contents can be read but not written or erased. 2. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 1. all other addresses are low. 3. vid is the silicon-id-read high voltage, 11.5v to 13v. 4. read operations with vpp = vpph may access array data or silicon id codes. 5. with vpp at high voltage, the standby current equals icc + ipp (standby). 6. refer to table 1 for valid data-in during a write operation. 7. x can be vil or vih. 8. includes d15 pins a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code(hex) code byte manufacture code vilvil--------- --- ---------11000010 c2h = l device code vihvil--------- --- ---------00101011 2bh byte manufacture code vil0 0 0 0 0 0 0 011000010 00c2h = h device code vih0 0 0 0 0 0 0 000101011 002bh table 3. silicon id code
7 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 erase-verify command after each erase operation, all bytes must be verified. the erase verify operation is initiated by writing xxa0h into the command register. the address for the byte to be verified must be supplied as it is latched on the falling edge of the we pulse. the mx28f2100b applies an internally generated margin voltage to the addressed byte. reading ffffh from the addressed byte indicates that all bits in the byte are erased. the erase-verify command must be written to the command register prior to each byte verification to latch its address. the process continues for each byte in the array until a byte does not return ffffh data, or the last address is accessed. in the case where the data read is not ffffh, another erase operation needs to be performed. (refer to set- up erase/erase). verification then resumes from the address of the last-verified byte. once all bytes in the array have been verified, the erase step is complete. the device can be programmed. at this point, the verify operation is terminated by writing a valid command (e.g. program set-up) to the command register. the high reliability erase algorithm illustrates how commands and bus operations are combined to perform electrical erasure of the mx28f2100b. set-up automatic chip erase/erase commands the automatic chip erase does not require the device to be entirely pre-programmed prior to excuting the automatic set-up erase command and automatic chip erase command. upon executing the automatic chip erase command, the device automatically will program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. the erase and verify operations are completed by the feed back of the status register. the system is not required to provide any control or timing during these operations. read command while v pp is high, for erasure and programming, memory contents can also be accessed via the read command. the read operation is initiated by writing xxffh into the command register. microprocessor read cycles retrieve array data. the device remains enabled for reads until the command register contents are altered. reset command a reset command is provided as a means to safely abort the erase- or program-command sequences. following set-up command with two consecutive writes of xxffh for ers (or one write of xxffh for pgm) will safely abort the operation. memory contents will not be altered. a valid command must then be written to place the device in the desired state. silicon-id-read command flash-memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer- and device-codes must be accessible while the device resides in the target system. prom programmers typically access signature codes by rais- ing a9 to a high voltage. however, multiplexing high voltage onto address lines is not a desired system- design practice. the mx28f2100b contains a silicon-id-read operation to supplement traditional prom- programming methodology. the operation is initiated by writing xx90h into the command register. following the command write, a read cycle with a0=vil retrieves the manufacturer code of c2h(byte=vil, 00c2h(byte=vih). a read cycle with a0=vih returns the device code of 2bh(byte = vil), 002bh(byte = vih).
8 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required). the margin voltages are internally generated in the same manner as when the standard erase verify command is used. if the erase operation was unsuccessful, bit 5 of the status register will be set to a "1", indicating an erase failure. if vpp was not within acceptable limits after the erase command is issued, the state machine will not execute an erase sequence; in stead, bit 5 of the status register is set to a "1" to indicate an erase failure, and bit 3 is set to a "1" to indentify that vpp supply voltage was not within acceptable limits. the automatic set-up erase command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. automatic set-up erase is performed by writing xx30h to the command register. to commence automatic chip erase, the command xx30h must be written again to the command register. set-up automatic block erase/erase commands the automatic block erase does not require the device to be entirely pre-programmed prior to executing the automatic set-up block erase command and automatic block erase command. upon executing the automatic block erase command, the device automatically will program and verify the block(s) memory for an all-zero data pattern. the system is not required to provide any controls or timing during these operations. when the block(s) is automatically verified to contain an all-zero pattern, a self-timed block erase and verify begin. the system is not required to provide any control or timing during these operations. when using the automatic block erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). the margin voltages are internally generated in the same manner as when the standard erase verify command is used. the automatic set-up block erase command is a com- mand only operation that stages the device for auto- matic electrical erasure of selected blocks in the array. automatic set-up block erase is performed by writing xx20h to the command register. to enter automatic block erase, the user must write the command d0h to the command register. block addresses selected are loaded into internal register on the second falling edge of we. each successive block load cycle started by the falling edge of we must begin within 30us from the rising edge of the preceding we. otherwise, the loading period ends and internal auto block erase cycle starts. erase suspend this command only has meaning while the state ma- chine is executing automatic chip/block erase opera- tion, and therefore will only be responded to during automatic chip/block erase operation. it is noted that erase suspend is meaningful for block erase only after block addresses load are finished (100 us after the last address is loaded). after this command has been ex- ecuted, the command register will initiate erase sus- pend mode. the state machine will set dq7, dq6 as 1, 1, after suspend is ready. at this time, state machine only allows the command register to respond to the read memory array, erase resume and read status register.
9 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 set-up automatic program/program commands the automatic set-up program is a command only operation that stages the device for automatic pro- gramming. automatic set-up program is performed by writing xx10h/xx40h to the command register. program command is the command for byte-program or word-program. once the automatic set-up program operation is per- formed, the next we pulse causes a transition to an active programming operation. addresses are latched on the falling edge, and data are internally latched on the rising edge of the we pulse. the rising edge of we also begins the programming operation. the system is not required to provide further controls or timings. the device will automatically provide an adequate internally generated program pulse and verify margin. if the program opetation was unsuccessful, bit 4 of the status register will be set to a "1", indicating a program failure. if vpp was not within acceptable limits after the program command is issued, the state machine will not execute a program sequence; in stead, bit 4 of the status register is set to a "1" to indicate a program failure, and bit 3 is set to a "1" to identify that vpp supply voltage was not within acceptable limits. status register the device contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status command to the command interface. after writing this command, all subsequent read operations output data from the status register until another command is written to the command interface. a read array command must be written to the command interface to return to the read array mode. erase resume this command will cause the command register to clear the suspend state and set dq6, dq7, back to 0, 0, but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. the status register bits are output on dq[0:7], whether the device is in the byte-wide (x8) or word- wide (x16) mode. in the word-wide mode the upper byte, dq[8:15], is set to 00h during a read status command. in the byte-wide mode, dq[8:14] are tri- stated and dq15/a-1 retains the low order address function. the contents of the status register are latched on the falling edge of oe or ce, whichever occurs last in the read cycle. this prevents possible bus errors which might occur if the contents of the status register change while reading the status register. ce or oe must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident from the status register. when the state machine is active, this register will indicate the status of the state machine, and will also hold the bits indicating whether or not the state machine was successful in performing the desired operation. clearing the status register the state machine sets status bits "3" through "7" to "1", and clears bits "6" and "7" to "0", but cannot clear status bits "3" through "5" to "0". bits 3 through 5 can only be cleared by the controlling cpu through the use of the clear status register command. these bits can indicate various error conditions. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). the status register may then be read to determine if an error occurred during that programming or erasure series. this adds flexibility to the way the device may be programmed or erased. once an error occured, the command interface only responds to clear status register, read status register and read array. to clear the status register, the clear status register command is written to the command interface. then, any other command may be issued to the command interface. note, again, that before read cycle can be initiated, a read array command must be written to the command interface to specify whether the read data is to come from the memory array, status register, or sili-con -id.
10 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 status register bit definition sr.7 = write state machine status(wsms) 1 = ready 0 = busy sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed sr.5 = erase status 1 = error in erase 0 = successful erasure sr.4 = program status 1 = error in byte/word program 0 = successful byte/word program sr.3 = vpp status 1 = vpp low detect, operation abort 0 = vpp ok note : state machine bit must first be checked to determine byte/word program or block erase completion, before the program or erase status bits are checked for success. when erase suspend is issued, state machine halts execution and sets both wsms and ess bits to "1," ess bit remains set to "1" until an erase resume command is issued. when this bit set to "1," state machine has applied the maximum number of erase pulses to the device and is still unable to successfully verify erasure. when this bit is set to "1," state machine has attempted but failed to program a byte or word. the vpp status bit, unlike an a/d converter, does not provide continuous indication of vpp level. the state machine interrogates vpp level only after the byte write or erase command sequences have been entered, and informs the system if vpp has not been switched on. wsms ess es ps vpps 7 6 5 4 3
11 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 data protection the mx28f2100b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. low vpp write inhibit to avoid initiation of a write cycle during v pp power-up and power-down a write cycle is locked out for v pp less than v pplk (typically 9v). if v pp < v pplk , the command register is disabled and all internal program/erase circuits are disabled. subsequent writes will be ignored until the v pp level is greater than v pplk . it is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when v pp is above v pplk . logical inhibit writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power supply decoupling in order to reduced power switching effect, each device should have a 0.1uf ceramic capacitor connected between its vcc and gnd, and between its vpp and gnd. vpp trace on printed circuit board programming flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the vpp power supply trace. the vpp pin supplies the memory cell current for programming. use similar trace widths and layout considerations given to the vcc power bus. adequate vpp supply traces and decoupling will decrease vpp voltage spikes and overshoots. deep power down mode this mode is enabled by rp pin. during read modes, rp going low deselects the memory and place the output drivers in a high-z state. in erase or program modes, rp low will abort erase or program operations, but the memory contents are no longer valid as the data has been corrupted by rp function. rp transition to vil, or turning power off to the device will clear up status register and automatically defaults to the read array mode. power-up sequence the mx28f2100b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of a two-step command sequence. vpp and vcc power up sequence is not required. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce or we will not initiate a write cycle.
12 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 absolute maximum ratings rating value ambient operating temperature 0 o c to 70 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 & vpp & rp -0.5v to 13.5v notice: stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operational sections of this specification is not implied. exposure to ab- solute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are sub- ject to change. switching vcc voltages vcc supply switching timing symbol parameter min. max. unit t5vph vcc at 4.5v (minimum) to rp high 3 ms notice: the t5vph time must be strictly followed to guarantee all other read and write specifications. vcc supply switching waveform capacitance ta = 25 o c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 8 pf vin = 0v cout output capacitance 12 pf vout = 0v t5vph 5.0v vcc gnd vih rp vil
13 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 read operation dc characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp = gnd to vcc symbol parameter min. typ max. unit conditions ili input leakage current 1 ua vin = gnd to vcc ilo output leakage current 10 ua vout = gnd to vcc ipp1 vpp current 1 100 ua vpp = 5.5v isb1 standby vcc current 1 ma ce = vih isb2 1 100 ua ce = vcc + 0.3v icc1 operating vcc current 50 ma iout = 0ma, f=1mhz icc2 70 ma iout = 0ma, f=10mhz vil input low voltage -0.3 (note 1) 0.8 v vih input high voltage 2.0 vcc + 0.3 v vol output low voltage 0.45 v iol = 2.1ma voh output high voltage 2.4 v ioh = -400ua notes: 1. vil min. = -1.0v for pulse width < 50 ns. vil min. = -2.0v for pulse width < 20 ns. 2. vih max. = vcc + 1.5v for pulse width < 20 ns if vih is over the specified maximum value, read operation cannot be guaranteed. ac characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp = gnd to vcc 28f2100b-70 28f2100b-90 28f2100b-12 symbol parameter min. max. min. max. min. max. unit conditions tacc address to output delay 70 90 120 ns ce=oe=vil tce ce to output delay 70 90 120 ns oe=vil toe oe to output delay 30 40 50 ns ce=vil tdf oe high to output float ( note1) 0 20 0 30 0 30 ns ce=vil toh address to output hold 0 0 0 ns ce=oe=vil note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: ? input pulse levels: 0.45v/2.4v ? input rise and fall times: < 10ns ? output load: 1 ttl gate + 35pf (including scope and jig) ? reference levels for measuring timing: 0.8v, 2.0v
14 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 byte read timing waveforms word read timing waveforms a-1~16 ce oe tacc we vih vil vih vil vih vil vih vil vih vil voh vol high z high z data valid toe tdf tce byte data q0~7 high z high z voh vol data q8~14 toh add valid rp a0-16 ce oe tacc we vih vil vih vil vih vil vih vil vih vil voh vol standby mode standby mode high z high z data valid toe tdf tce toh byte data q0-15 active mode add valid rp
15 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 dc characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp = 12v 7% symbol parameter min. typ max. unit conditions ili input leakage current 1 ua vin=gnd to vcc ilo output leakage current 10 ua vout=gnd to vcc isb1 standby vcc current 1 ma ce=vih isb2 1 100 ua ce=vcc 0.3v icc1 (read) operating vcc current 50 ma iout=0ma, f=1mhz icc2 70 ma iout=0ma, f=10mhz icc3 (program) 50 ma in programming icc4 (erase) 50 ma in erase icces vcc erase suspend current 10 ma ce=vih, erase suspended ipp1 (read) vpp current 200 ua vpp=12.8v ipp2 (program) 50 ma in programming ipp3 (erase) 50 ma in erase vil input voltage -0.3 (note 5) 0.8 v vih 2.0 vcc+0.3v v (note 6) vol output voltage 0.45 v iol=2.1ma voh 2.4 v ioh=-400ua vpplk vpp lockout voltage 0.0 6 v vpph vpp for program/erase operation 11.16 12.84 v 12v 7% command programming/data programming/erase operation notes: 1. vcc must be applied before vpp and remove after vpp. 2. vpp must not exceed 14v including overshoot. 3. an influence may be had upon device reliability if the device is installed or removed while vpp=12v. 4. do not alter vpp either vil to 12v or 12v to vil when ce=vil. 5. vil min. = -0.6v for pulse width < 20ns. 6. if vih is over the specified maximum value, programming operation cannot be guranteed. 7. icces is specified with the device de-selected. if the device is read during erase suspend mode, current draw is the sum of icces and icc1 or icc2. 8. all current are in rms unless otherwisw noted.
16 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 ac characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp =12v 7% 28f2100b-70 28f2100b-90 28f2100b-12 symbol parameter min. max. min. max. min. max. unit conditions tvps vpp setup time 100 100 100 ns tphel 1000 1000 1000 ns toes oe setup time 100 100 100 ns tcwc command programming cycle 70 90 120 ns tcep we programming pulse width 50 50 50 ns tceph1 we programming pluse width high 20 20 20 ns tceph2 we programming pluse width high 100 100 100 ns tas address setup time 0 0 0 ns tah address hold time 45 50 50 ns tds data setup time 45 50 50 ns tdh data hold time 10 10 10 ns tces ce setup time 0 0 0 ns tcesc ce setup time before command write 100 100 100 ns tcesv ce setup time before verify 6 6 6 us tvph vpp hold time 100 100 100 ns tdf output disable time (note 2) 20 30 30 ns tva verify access time 70 90 120 ns taetc total erase time in auto chip erase 5(typ.) 5(typ.) 5(typ.) s taetb total erase time in auto block erase 1(typ.) 1(typ.) 1(typ.) s tavt total programming time in auto verify 50 1600 50 1600 50 1600 us tet standby time in erase 10 10 10 ms tbalc block address load cycle 0.3 30 0.3 30 0.3 30 us tbal block address load time 100 100 100 us tch ce hold time 0 0 0 ns tcs ce setup to we going low 0 0 0 ns notes: 1. ce and oe must be fixed high during vpp transition from 5v to 12v or from 12v to 5v. 2. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven. 3. tphel: rp high recovery to ce going low: 500ns, max 1000ns.
17 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 switching test circuits switching test waveforms device under test diodes=in3064 or equivalent cl 6.2k ohm 1.8k ohm +5v cl=35pf including jig capacitance 2.0v 2.4 v 0.45 v 0.8v test points input 2.0v 0.8v output ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are <20ns.
18 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 command write timing waveform-byte mode add a-1 -16 ce oe we din tds tah byte data q0-7 tdh tcs tch tcwc tceph1 tcep toes tas tvps data q8-14 vcc vpp 5v 12v ov note: byte pin is treated as address pin. all timing specifications for byte pin are the same as those for address pin. vih vil vih vil vih vil vih vil vih vil vih vil vih vil high z add valid rp tphel
19 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 command write timing waveform-word mode a0-16 ce oe we din tds tah byte data q0-15 tdh tcs tch tcwc tceph1 tcep toes tas tvps vcc vpp 5v vih vil 12v ov vih vil vih vil vih vil vih vil vih vil add valid tphel rp
20 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic programming timing waveform one byte data is programmed. verify in fast algorithm and additional programming by external control are not required because these operations are excuted auto- matically by internal control circuit. programming completion can be verified by status register after automatic program starts. automatic programming timing waveform-byte mode tcwc tas tcep toes tcep tces tds tdh tdh tds tdf vcc 5v ce oe 12v vpp 0v tvph data q0~q2 we add a-1~16 tceph1 tvps din valid srd tcs tcs tch tch add valid tcesc vih vil byte data q3~q7 data q8~q14 vih vil vih vil vih vil vih vil vih vil vih vil vih vil din command in high z tcesp 10h/or 40h rp tphel command in
21 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic programming timing waveform-word mode din tcwc tas tcep toes tcep tces tds tdh tdh tds tdf vcc 5v ce oe 12v vpp 0v tvph data q0~q2 setup auto program/ program command vaild srd we add a0~16 tceph1 tah1 tdpa tvps din din tcs tcs tch tch add valid tcesc vih vil byte data q3~q7 data q8~q15 vih vil vih vil vih vil vih vil vih vil vih vil vih vil tcesp command in 10h/or 40h tvps rp command in
22 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 program command sequence (address/command) automatic programming algorithm flowchart start apply vpph write set up auto program command (10h/40h) read status register write auto program command(a/d) status register ready full status check vpp range error yes 1 no sr.7=1 sr.3= sr.4= 00 1 program error programming successfully
23 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic chip erase timing waveform all data in chip are erased. external erase verify is not required because data is erased automatically by internal control circuit. erasure completion can be verified by status register contents after automatic erase starts. automatic chip erase timing waveform-byte mode tcwc tcep toes tcep tces tds tdh tdh tds tdf vcc 5v ce oe 12v vpp 0v tvph data q0~q2 auto erase setup auto chip erase/ erase command we add a-1~16 tceph1 tdpa tvps vaild srd tcs tcs tch tch tcesp tcesc vih vil byte data q3~q7 data q8~q14 taetc command in note: erase suspend and read array modes are not included in this waveform. vih vil vih vil vih vil vih vil vih vil vih vil vih vil 30h 30h high z command in command in command in rp tphel
24 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic chip erase timing waveform-word mode tcwc tcep toes tcep tces tds tdh tdh tds tdf vcc 5v ce oe 12v vpp 0v tvph data q0~q3 auto erase setup auto chip erase/ erase command we add a0~16 tceph1 tdpa tvps valid srd tcs tcs tch tch tcesp tcesc vih vil byte data q7 data q8~q15 command in note: erase suspend and read array modes are not included in this waveform. vih vil vih vil vih vil vih vil vih vil vih vil vih vil 30h 30h command in command in command in rp tphel
25 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic chip erase algorithm flowchart start apply vpph write set up auto chip erase command (30h) 0 read status register write auto chip erase command(30h) sr.7= operation done. device stays at read status register mode to check sr3, 4, 5 to see whether erase successfully 1 chip erase completed to execute suspend mode no yes erase suspend/ erase resume flow
26 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic block erase timing waveform block data (refer to page 1 for block structure) are erased. external erase verify is not required because data are erased automatically by internal control circuit. erasure completion can be verified by status register contents after automatic erase starts. automatic block erase timing waveform-byte mode vcc 5v tcep toes tdf command in oe command in command in command in tcesc tds tdh tds tdh block address 0 block address 1 tcwc tbalc tcep 12v vpp 0v block address # command #20h command #d0h tvph tbal taetb q3~q7 q0~q2 auto block erase & status register read a-1~ a16 ce we tceph2 tceph1 setup auto block erase/erase command tvps tah tas pbyte vih vil vih vil vih vil vih vil vih vil vih vil vih vil rp tphel valid data
27 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic block erase timing waveform-word mode vcc 5v tcep toes command in oe command in command in command in tcesc tds tdh tds tdh block address 0 block address 1 tcwc tbalc tcep 12v vpp 0v block address # command #20h command #d0h tvph tvps tbal q0~q2 auto block erase a0 ~ a16 ce we tceph2 tceph1 setup auto block erase/erase command tah tas byte vih vil vih vil vih vil vih vil vih vil vih vil vih vil valid srd q3~q7 vih vil rp tphel q8~q15
28 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 automatic block erase algorithm flowchart start apply vpph write set up auto chip erase command (20h) 0 read status register write auto chip erase command(d0h) sr.7= operation done. device stays at read status register mode to check sr3, 4, 5 to see whether erase successfully. 1 chip erase completed to execute suspend mode no yes erase suspend/ erase resume flow load other sectors address if necessary (load other sector address)
29 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 erase suspend/erase resume flowchart start write data b0h 1 read status register sr.7= 0 sr.6= 0 1 yes no erase completed check sr3, 4, 5 to see whether erase successfully write data ffh write data d0h continue erase reading end read array write ffh read array
30 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 fast high-reliability chip erase this device can be applied the fast high-reliability chip erase algorithm shown in the following flowchart. chip erase flow fast high-reliability chip erase flowchart command sequence start all bits end no yes fail all bits verified pgm "0" n = 0 chip erase flow ersvfy flow n = 1024? chip erase fail apply vpp = vcc chip erase complete n = n+1 start apply write setup chip erase command end vpp = vpph ( 20h ) write chip erase command ( 20h ) wait 10 ms
31 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 erase verify flow start write erase verify command wait 6 us last address ? increment address no yes no yes apply vpp = vpph address = first address of erased blocks or last verify failed address ( a0h ) ersvfy ffh ? erase verify complete go to erase flow again or abort
32 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 fast high-reliability chip erase timing waveform all data in chip are erased. control verification and additional erasure externally according to fast high-relia- bility chip erase flowchart. successful erasure comple- tion can be verified by status registers. fast high-reliability chip erase timing waveform-byte mode vcc 5v tcep toes tdf command in ce oe tcesc tcep tds tdh tds tdh tcwc tet tcep tces tva command in tds 12v vpp 0v command #20h command #20h command #a0h tvph tphel q0~q7 erase verify chip erase tas tah verify address tcesv command in tdh valid data a-1 ~ a16 we tceph1 setup chip erase/ erase command byte vih vil vih vil vih vil vih vil vih vil vih vil rp tvps
33 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 fast high-reliability chip erase timing waveform-word mode vcc 5v tcep toes tdf command in ce oe tcesc tcep tds tdh tds tdh tcwc tet tcep tces tva command in tds 12v vpp 0v command #20h command #20h command #a0h tvph tvps q0~q7 erase verify chip erase tas tah verify address tcesv command in tdh a0 ~ a16 we tceph1 setup chip erase/ erase command valid data byte vih vil vih vil vih vil vih vil vih vil vih vil q8~q15 vih vil rp tphel valid data
34 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 fast high-reliability block erase this device can be applied to the fast high-reliability block erase algorithm shown in the following flowchart. block erase flow fast high-reliability block erase flowchart command sequence start apply write setup block erase command end vpp = vpph write block erase command ( 60h ) wait 10 ms ( load first sector address , 60h ) load other sectors' address if necessary ( load other sector address ) start end no yes fail all bits verified n = 0 block erase flow ersvfy flow n = 1024? block erase fail apply vpp = vcc block erase complete n = n+1 for selected block(s), all bits pgm"0"
35 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 erase verify flow start write erase verify command wait 6 us last address ? increment address no yes no yes apply vpp = vpph address = first address of erased blocks or last verify failed address ( a0h ) ersvfy ffh ? erase verify complete go to erase flow again or abort
36 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 fast high-reliability block erase timing waveform indicated block data are erased. control verification and additional erasure externally according to fast high-reli- ability block erase flowchart. fast high-reliability block erase timing waveform-byte mode vcc 5v tds tdf command in tds tdh tds tdh tva command in command in tdh tbal tet tcep tas tah tcesc toes tcep tcep tcwc tbalc block address 0 block address 1 tas ce oe 12v vpp 0v command #60h command #60h command #a0h tvph q0~q7 erase verify block erase tcesv tces valid data verify address a-1 ~ a16 we block address # tceph1 tceph2 setup block erase/erase command tvps tah vih vil vih vil vih vil vih vil vih vil vih vil byte rp tphel
37 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 fast high-reliability block erase timing waveform-word mode vcc 5v tds tdf command in tds tdh tds tdh tva command in command in tdh tbal tet tcep tcesc toes tcep tcep tcwc tbalc block address 0 block address 1 tas ce oe 12v vpp 0v command #60h command #60h command #a0h tvph tvps q0~q7 erase verify block erase tcesv tces valid data verify address a0 ~ a16 we block address # tceph1 tceph2 setup block erase/erase command tah vih vil vih vil vih vil vih vil vih vil vih vil byte rp tphel
38 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 vpp high read timing waveform-byte mode vpp high read timing waveform-word mode tvps address valid tacc tvph tcesc tcwc toes tcep tce toes tdf toh tds tdh toe data valid vcc 5v 12v vpp 0v add a-1 ~16 ce oe data q0-7 ffh we tcs tch high-z vih vil vih vil vih vil vih vil vih vil vih vil vih vil data q8-q14 byte command in rp tphel tvps address valid tacc tvph tcesc tcwc toes tcep tce toes tdf toh tds tdh toe data valid vcc 5v 12v vpp 0v add a0 ~16 ce oe data q0-15 command in we tcs tch vih vil vih vil vih vil vih vil vih vil vih vil byte xx ffh rp tphel
39 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 vpp low id code read timing waveform-byte mode tacc tce tacc toe toh toh tdf data out c2h 2bh vid vih vil add a9 add a1-a16 ce oe we add a0 byte data out data q8-q14 data q0-q7 vcc 5v vih vil vih vil vih vil vih vil vih vil vih vil vih vil high-z vih vil add a-1 rp
40 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 vpp low id code read timing waveform-word mode tacc tce tacc toe toh toh tdf data out 00c2h 002bh vid vih vil add a9 add a1-a16 rp oe we add a0 byte data out data out data out data q8-q15 data q0-q7 vcc 5v vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil ce
41 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 vpp high id code read timing waveform-byte mode tcwc tvps address valid 0 or 1 tacc tvph tcesc toes tcep tce toes tdf toh tds tdh toe data out vcc 5v 12v vpp 0v ce oe data q0-q7 command in c2h or 2bh add a1-a16 we tcs tch data q8-q14 add a-1 add a0 byte high-z vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil vih vil 90h rp tphel
42 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 vpp high id code read timing waveform-word mode tcwc tvps address valid 0 or 1 tacc tvph tcesc toes tcep tce toes tdf toh tds tdh toe data out vcc 5v 12v vpp 0v ce oe data q0-q15 command in 00c2h or 002bh add a1-a16 we tcs tch add a0 byte vih vil vih vil vih vil vih vil vih vil vih vil vih vil note: byte pin is treated as address pin all timing specifications for byte pin are the same as those for address pin. xx90h rp tphel
43 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 ordering information plastic package part no. access time operating current standby current package (ns) max.(ma) max.(ua) mx28f2100bmc-70 70 50 100 44 pin sop mx28f2100bmc-90 90 50 100 44 pin sop mx28f2100bmc-12 120 50 100 44 pin sop mx28f2100btc-70 70 50 100 48 pin tsop (normal type) MX28F2100BTC-90 90 50 100 48 pin tsop (normal type) mx28f2100btc-12 120 50 100 48 pin tsop (normal type) revision history rev. # description date 1.4 statement cleared for customer's better understanding 10/22/1997
44 mx28f2100b p/n: pm0382 rev. 1.5, mar. 24, 1998 package information 44-pin plastic sop(500 mil) item millimeters inches a 28.70 max. 1.130max. b 1.10 [ref] .043 [ref] c 1.27 [tp] .050 [tp] d .40 .10[typ.] .016 .004[typ.] e .010 min. .004 min. f 3.00 max. .118 max. g 2.80 .13 .110 .005 h 16.04 .30 .631 .012 i 12.60 .496 j 1.72 .068 k .15 .10 [typ.] .006 .004[typ.] l .80 .20 .031 .008 note: each lead certerline is located within .25mm[.01 inch] of its true position [tp] at a maximum at maximum material condition. item millimeters inches a 20.0 .20 .787 .008 b 18.40 .10 .724 .004 c 12.20 max. .480 max. d 0.15 [typ.] .006 [typ.] e .80 [typ.] .031 [typ.] f .20 .10 .008 .004 g .30 .10 .012 .004 h .50 [typ.] .020 [typ.] i .45 max. .018 max. j 0 ~ .20 0 ~ .008 k 1.00 .10 .039 .004 l 1.27 max. .050 max. m .50 .020 n 0 ~5 .500 note: each lead certerline is located within .25mm[.01 inch] of its true position [tp] at a maximum at maximum material condition. 48-pin plastic tsop a b c d e f g h i j kl m n 122 23 44 a dc b e gf h i j k l
45 mx28f2100b m acronix i nternational c o., l td. headquarters: tel:+886-3-578-8888 fax:+886-3-578-8887 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-747-2309 fax:+65-748-4090 taipei office: tel:+886-3-509-3300 fax:+886-3-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the rignt to change product and specifications without notice.

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